1. Field of the Invention
Embodiments of the present invention relate, in general, to cross-coupling Peripheral Component Interconnect express (“PCIe”) switches and particularly to cross-coupling PCIe switches using non-transparent PCIe switch ports.
2. Relevant Background
Typical current computer system configurations consist of one or more processor and Input/Output (“I/O”) complexes connected through internal high speed busses. This connection occurs via I/O adapter cards, commonly termed Host Bus Adapters (HBAs) or Network Interface Cards (NICs). The highest performance systems, as is currently known in the art, use a PCI express bus as the interface to a HBA or NIC bus, as shown in FIG. 1.
Microprocessor complexes in many such systems provide several I/O busses, which may either be connected directly to an HBA, or connected to several HBAs through an I/O switch. The collection of busses and switches is often termed an I/O switching fabric or complex. As illustrated in FIG. 1, a PCIe switch 110 forms, in one example, a tree of devices owned by one microprocessor (CPU) complex 120 at the root of the tree. The microprocessor complex 120 of FIG. 1 is connected directly to a single HBA 130 as well as the PCIe switch 110 which is in turn coupled to two other HBA devices 140, 150 and a NIC 160, the NIC 160 providing access to a network 170. Two arrays 180, 190 are connected to the microprocessor complex 120 via the PCIe switch 110/HBA 140 path or directly through a single HBA 130. Currently, no mechanism exists with standard PCI devices and switches to share a device with multiple CPU complexes.
Microprocessor complexes and devices in two PCI trees can talk to each other using a non-transparent bridge. Such a bridge consists of two ports, both of which appear to be PCI leaf devices. As a PCI device, they respond to specific, programmable address ranges. Unlike normal devices, when they detect a PCI transaction in their address range, they pass the transaction on to the other port, after adding or subtracting an address offset, and essentially place the request on the other PCI tree. This allows hosts and devices in one tree to access memory locations and device registers in the other tree.
Non-transparent bridges, as is known in the prior art, can also be built directly into ports of PCIe switches, as illustrated in FIG. 2. As shown in FIG. 2, a multi-port PCIe switch 210, associated with a first microprocessor complex 220, is shown with one non-transparent port 230 connected to a second microprocessor complex 240. This allows both microprocessor complexes 220, 240 to access the registers and memory on the I/O devices 250, and allows the I/O devices 250 to access the main memories in both microprocessor complexes 220, 240. However, in this example, all I/O devices 250 are controlled by the first microprocessor complex's 220 operating system. This can result in placing an excessive workload on the first microprocessor complex, and leaves the system vulnerable to the failure of the first microprocessor complex. If the first microprocessor complex does fail, the second microprocessor complex 240 can reprogram the switch 210 to move the non-transparent port to the second microprocessor complex 240 effectively giving it control and allowing processing to resume after a brief pause.
Each of the I/O devices 250 controlled by the first microprocessor complex 220 can access the memory of either microprocessor complex 220, 240 through an access address. For example, assume each microprocessor complex 220, 240 has one Gigabyte (1 GB) of main memory, addressed from location zero. The non-transparent port 230 can be configured to pass all addresses below 1 GB to the first microprocessor complex 220, and to pass all addresses above 1 GB to the second microprocessor complex 240, after first subtracting 1 GB from the address. Thus both microprocessor complexes 220, 240 see addresses in the correct range, and the second microprocessor complex 240 does not need to be aware that the requests originated with a different address range.
As many computer systems, and the storage devices connected to them, are expected to maintain a very high state of availability, it is typically expected that the systems continue to run even when a component fails. The current approach to achieving high availability is to provide redundant components and paths. One way to achieve this in a storage subsystem is to provide each device and host with at least two ports, and provide each with at least two storage switches such as a Fibre-Channel Switch.
An example using a Fibre-Channel (“FC”) as an array interconnect, as is known in the prior art, is shown in FIG. 3. Note that each host 310, 320 has two paths to each array 350, 360, so when a switch or FC cable becomes inoperative, the affected host can still communicate with the array or arrays over the other path or paths. The traditional redundant array and switch approach uses alternate paths to provide high storage availability. As configured, it is possible for both hosts to access both arrays, so when provisions are made to store data redundantly on the arrays then the system can continue to operate even when an array fails, and when appropriate software and network connections (not shown) are installed on the hosts 310, 320, the basic applications may continue to run even when one host fails. This approach to high availability is widely used in the computer industry.
As is known in the prior art, other operations along with the switching, such as file services or storage virtualization are often desired. In those cases the switches are replaced by storage processors, and often combined into what is commonly referred to as a storage appliance. Within a storage appliance, it is still necessary to have at least two independent storage processors in order to achieve high availability. The storage processors typically run separate instances of an operating system or other code. Typically, there is also a pair of inter-processor links which provides communication between the processors. These links can optionally include switches and additional links to additional storage processors for capacity expansion.
For a number of reasons many of the offered I/O requests and associated data may have to be processed by two or more storage processors and hence travel across the inter-processor links. This can occur with larger configurations because a given host and array may not be connected to the same set of storage processors. Even if they are, requests still may have to be forwarded across the inter-processor links because the other storage processor must participate in the operation.
Just as cross-coupling hosts, switches and storage devices can increase capacity and provide higher availability in a FC storage network, so can cross-coupling switches within a multi-processor. Multistage switching allows capacity expansion by adding extra columns and rows to the switch matrix. If link bandwidth utilization is well balanced you can achieve a near linear increase in total system bandwidth as you increase the system size, at a significant savings in switch elements over those required by a full crossbar switch.
As shown in FIG. 4, by adding an extra stage (row) of switches, a second path can be created between each microprocessor 410 and each memory device 440. These redundant paths provide the benefits of improved availability and traffic spreading. Careful examination of FIG. 4 will reveal that all combinations of any microprocessor 410 and any memory device 440 access, have two independent paths through the switch matrix 450, allowing full connectivity to continue even if one switch fails.
Each of the aforementioned techniques however, possesses significant drawbacks. While each of the previously described techniques provide access to all of the attached devices, the access is not equal, balanced, or independent. Hosts, or microprocessor complexes, of the systems previously described expect to have exclusive control of the drives to which they have access, thus in a large computing environment having multiple hosts, cross connectivity results in hosts fighting over which host owns and controls the data on any one particular device. These and other problems are addressed by embodiments of the present invention as described by example in the following detailed description.